The present invention generally relates to an integrated circuit apparatus having timing control circuits for delaying inputted digital signals by a constant time under a certain control so as to output them, and more particularly, even among them, to a timing control circuit to be used when the delay of the signals is controlled dynamically in a phase locked loop (PLL).
In a microprocessor and its peripheral system having an operation frequency exceeding 40 MHz, a synchronous interface with a high bus-band-width is demanded so as to obtain a high performance. Especially when the bus clock becomes 25 ns or lower, the skew existence between an internal clock and a bus clock of the function device cannot be neglected with respect to the bus clock despite the synchronous operation of the respective function devices (especially integrated circuits) with the bus clock. The higher speed (especially retention of setup time and hold time) of the access to the memory subsystem becomes difficult to effect.
Influences upon the setup time and the hold time by the skew existence between the internal clock and the bus clock of the above described function device will be described in one example with reference to the drawings.
FIG. 11 shows the relationship between the reading data from the memory subsystem synchronized with the bus clock and the internal clock of the function device. Here all the timings are prescribed with respect to the rising edge of the bus clock. Assume that the setup time of the reading data with respect to the rising edge of the bus clock is d1, and the hold time is d2. Further, the reading data are adapted to be sampled with a rising edge of the internal clock.
When the internal clock is delayed by time d with respect to the bus clock as shown in FIG. 11 (a), the hold time with respect to the rising edge of the internal clock becomes (d2-d). When the value is deviated from the specification of the functional device, the reading data cannot be sampled correctly any more in the function device. Such a situation is caused in a function device for generating, operating the internal clock from the bus clock. Generally, the minimum value of the hold time is often prescribed to be ONs. The hold time with respect to the bus clock becomes necessary to be at least 3 through 5 ns or so if d=3 through 5 ns although it is the amount of the load of the internal clock.
When the bus clock is delayed by time d with respect to the internal clock as shown in FIG. 11 (b), the setup time with respect to the rising edge of the internal clock becomes d1-d. When the value is deviated from the specification of the functional device, the reading data cannot be sampled correctly any more in the function device. Such a situation is caused in a function device for generating the bus clock from the internal clock so as to feed it. Generally the maximum value of the setup time is desired to be 3 ns or so. The setup time with respect to the bus clock becomes necessary to be at least 5 through 10 ns or so if d=5 through 10 ns although it depends upon the size of the bus load.
A margin considering the time difference d of the internal clock with respect to the bus clock is necessary to be provided with respect to the setup time d1 and the hold time d2 of the reading data with respect to the rising edge of the bus clock. This makes it difficult to have the higher speed of the access to the memory subsystem.
In order to obtain the high performance with these clock skews being made as small as possible, the phase locked loop (PLL) for controlling the phase is used with the use of the timing control circuit with an eye to making the skew between the internal clock of the function device and the bus clock as small as possible.
One conventional example of the phase locked loop (PLL) for controlling the phase with the use of the timing control circuit will be described hereinafter with reference to the drawings.
FIG. 12 is one conventional embodiment of the phase locked loop (PLL) for controlling the phase with the use of the timing control circuit. In FIG. 12, the signal delaying circuit 30 is composed of the series connection of a plurality of delay circuit elements with the clock signals 32 being made as input signals, signals with clock signals 32 being delayed are outputted as delay clock signals 34 from the output of the respective delay circuit elements. One of these delay clock signals 34 is selected by a selecting circuit 40 and is given to an internal clock generating circuit 110. A bus control circuit 112 generates an internal bus clock 114 by an internal clock 48 to be caused. A bus clock 116 is a clock having twice a period of the clock signals 32, is inputted to the phase detecting circuit 120 together with the internal bus clock 114 so as to produce the phase control signal 122 corresponding to the phase difference. The phase control signal 122 is inputted to a shift control circuit 124, the shift control circuit 124 controls the shift operation of a bi-directional shift register circuit 50 and the bi-directional shift register circuit 50 controls the selecting circuit 40.
A signal delay circuit 30, a selecting circuit 40, a bi-directional shift register circuit 50, a bus control circuit 112, an internal clock generating circuit 110, a phase detecting circuit 120, a shift control circuit 124 compose a phase locked loop (PLL). The phase detecting circuit 120 generates a phase control signal 122 corresponding to the phase difference between the internal bus clock 114 and the bus clock 116. The shift control circuit 124 shifts the set bit of the bi-directional shift register circuit 50 with the use of the phase control signal 122. The set bit exists in the only register within the bi-directional shift register circuit 50 with the others being reset bits. The set bit and the reset bit become control signals of the selecting circuit 40 so as to select the delay clock signal 34 of the signal delay circuit 30 corresponding to the set bit. The delay 10 clock signal 34 of the signal delay circuit 30 corresponding to the reset bit is not selected. The delay of the clock signal 32 is selected so that the phase difference of the internal bus clock 114 with respect to the bus clock 116 may become minimum. For example, when the internal bus clock 114 is delayed with respect to the bus clock 116, a delay clock signal 34 which is small in delay is selected with the use of the selecting circuit 40 and the bi-directional shift register circuit 50 so as to advance the internal bus clock 114. When the internal bus clock 114 advances with respect to the bus clock 116, the delay clock signal 34 large in the delay is selected with the use of the selecting circuit 40 and the bi-directional shift register circuit 50 so as to delay the internal bus clock 114.
The controlling operation is effected so that the phase of the internal bus clock 114 may be brought into conformity with respect to the bus clock 116 so as to minimum the skew between the clocks. One realizing example of such phase locked loop (PLL) is described in "The 68040 32-b Monolithic Processor (IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, Oct. 1990, p1178-1180)."
But the above described construction has such problems as described hereinafter.
(1) As the delay of the respective delay circuit elements for constituting the signal delay circuit 30 is constant, it is difficult to change the range and accuracy of the phase control. In order to solve the problems, it is easily supposed that the delay of the delay circuit element for constituting the signal delay circuit 30 has only to be varied so as to change the phase range and accuracy by the situation of the phase control. Unless a means of precisely grasping the situation of the phase control is realized, the range and the accuracy of the phase control cannot be change easily. PA1 (2) There is no means to know whether or not the delay necessary to the phase synchronous operation is in the delay to be controlled by the signal delay circuit 30.
(3) Two types of clock signals (bus clock and clock having frequencies twice as many as it) are used so as to simplify the phase synchronization. When only the bus clock is used (when the frequency of the bus clock itself is sufficiently high, the clock having frequency twice as many as it is hard to use), the phase of the bus clock is necessary to be delayed by 360.degree. (180.degree. when the logic has been inverted by a logic inverting circuit). To cope with the wide frequency range, the delay becomes insufficient in the signal delay circuit 30 only, thus making it impossible to effect a controlling operation.